1. Field of the Invention
The present invention is related to a shift register, and more particularly, to a shift register of gate driving circuit.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a prior art display panel 100. The display panel 100 includes a gate driving circuit 102 and a pixel array 112. The gate driving circuit 102 includes a plurality of shift registers. Each stage of shift register outputs a gate signal to the pixel array 112 in sequence through scanning lines 110 respectively.
FIG. 2 is a timing diagram illustrating the gate driving circuit 102 of FIG. 1. For brevity, an (N−1) th shift register 104, an Nth shift register 106, and an (N+1)th shift register 108 of FIG. 1 are taken as example in FIG. 2. In FIG. 2, the horizontal axis is time t, the vertical axis is voltage, and from top to bottom are a second clock signal XCK, a first clock signal CK, a gate signal Gn−1 outputted from the (N−1) th shift register 104, a gate signal Gn outputted from the Nth shift register 106, and a gate signal Gn+1 outputted from the (N+1) th shift register 108. During the T1 period, the second clock signal XCK switches from a low voltage to a high voltage and the (N−1) th shift register 104 outputs the high voltage to be the gate signal Gn−1 according to the second clock signal XCK. During the T2 period, the first clock signal CK switches from the low voltage to the high voltage and the Nth shift register 106 outputs the high voltage to be the gate signal Gn according to the first clock signal CK. During the T3 period, the second clock signal XCK again switches from the low voltage to the high voltage and the (N+1)th shift register 108 outputs the high voltage to be the gate signal Gn+1 according to the second clock signal XCK. Therefore, circuit nodes of the shift registers next to each other in the gate driving circuit 102 for receiving the second clock signal XCK and the first clock signal CK are arranged in alternating order to output gate signals respectively. Further the gate signal Gn+1 outputted from the (N+1) th shift register is outputted immediately after the gate signal Gn outputted from the Nth shift register, namely, the gate signal Gn+1's waveform is the gate signal Gn's waveform being shifted once.
However, for the gate signal Gn and the gate signal Gn+1 to be separated from each other by a half period of the first clock signal CK, namely, for the gate signal Gn+1's waveform to be the gate signal Gn's waveform shifted twice, components and wires of the Nth shift register 106 must be duplicated in layout. Further, in order for the gate signal of each stage of shift register to be separated from a preceding stage next to the stage of shift register by a half period of the first clock signal CK, each stage of shift register must be laid out twice, thereby increasing components number and layout area required by the gate driving circuit 102, which makes it harder to shrink display panel size.